Hello! I'm Jatan Mandaliya

As a passionate VLSI and hardware design enthusiast, I specialize in developing efficient and high-performance hardware solutions. With a strong foundation in ASIC workflow, physical design, FPGA-based system design, and static timing analysis, I excel at optimizing circuits for speed, power, and area. My expertise extends to designing and debugging embedded systems, ensuring seamless integration of hardware and software. Having participated in multiple hackathons and secured a win, I thrive on innovation and problem-solving, constantly pushing the boundaries of hardware optimization and next-generation semiconductor technologies.

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Years Experience

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Projects Completed

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Cups of Coffee Brewed

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Experience

January 2024 - May 2024 Embedded Hardware Intern

Tirex chargers

Designed and optimized PCB hardware for EV chargers using Altium, achieving a 15% size reduction through efficient component placement and routing while developing UPS logic with Op-Amps. Debugged and resolved 20+ design flaws related to signal integrity, power sequencing, and thermal management, enhancing system stability by 20%. Simulated Buck and Boost converters with PI control in MATLAB/Simulink and leveraged Machine Learning (ML) to accelerate parameter sweeps, ensuring less than 5% noise and stable load regulation.

January 2025 - Present Graduate Research Assistant

Nano-Electronics and Computing Research Lab - SFSU

Developed a Python framework to automate SPICE simulations for distributed RC networks, enabling efficient extraction of propagation delay, slew rate, and tail characteristics under varying resistance, capacitance, and segment configurations. Implemented an admittance propagation algorithm to generate reduced-order RC interconnect models (Pi Model) with less than 5% error compared to full RC network simulations. Performed transient and data sweep analyses in HSPICE to benchmark the accuracy of reduced-order Pi models against full RC tree models for interconnect delay estimation, identifying scenarios requiring higher-order models.

Education

2024-2026 Master's in Electrical and Computer Engineering

San Francisco State University

2020-2024 Bachelor's of Engineering in Electronics and Communications

Gujarat Technological University

Projects

16x18 SRAM Design using 14nm PDK

Designed a 16x18 SRAM using a 14nm PDK in Custom Compiler and WaveView, integrating a precharge circuit, write driver, sense amplifier, address decoder, and SRAM cell with an area-optimized schematic and layout. Conducted top-level functional verification, optimized access time and active power, and ensured design integrity by clearing LVS and DRC.

Motion Estimator in 14nm CMOS

Designed a Motion Estimator for video compression using the Block-Matching Algorithm, implementing Verilog modules such as Processing Elements, Comparator, and Controller with a pipelined architecture. Completed the full RTL-to-GDSII flow, including synthesis, place-and-route, area and power optimization, and ECO for hold violation correction.

MIPS32 Processor Design in 14nm CMOS

Designed a 5-stage pipelined MIPS32 processor in 14nm CMOS using Verilog, incorporating fetch, decode, execute, memory, and write-back stages with forwarding and hazard detection. Verified functionality with assembly-based testbenches and completed the full RTL-to-GDSII flow, including simulation, synthesis, constraint mapping, layout generation, and ECO implementation using VCS, Design Compiler, PrimeTime, and IC Compiler.

Wireless Communication on Spartan FPGA

Implemented SPI and I2C communication protocols on a Spartan FPGA for efficient peripheral data exchange and enabled RF-based wireless data transmission between two FPGAs using the NRF24L01 transceiver. Ensured seamless, low-latency communication, demonstrating expertise in FPGA-based system design.

Skills

Verilog

Python

TCL

C/C++

JavaScript

Physical Design

STA

Synopsys
EDA

JTAG

Linux

MATLAB

Machine
Learning

PCB Design

AWS

Contact Me

Get In Touch

Feel free to reach out to me for collaboration opportunities or any questions you may have.

Jatan Mandaliya
jatanmandaliya@gmail.com