Hello! I'm Jatan Mandaliya

Quantum Computing Inc - Hoboken, NJ

Developed hardware for high-speed power measurement for a Quantum Entropy Computer using NXP iMXRT 1060 (ARM Cortex-M7), achieving 10 MSPS sampling to capture precise power consumption data in real time. Built a DLL library in C/C++ to interface a parallel high-speed ADC, managing precise timers control, DMA, GPIO synchronization (DesOs), PCB design with safety isolation and EMI filtering principles under RF-critical constraints. Designed and tested the front-end hardware from component selection to PCB design in Altium Designer, obeying current testing and system-level debugging using oscilloscopes and logic analyzers, applied EMI-aware layout practices.

Tirex chargers

Designed and optimized PCB hardware for EV chargers using Altium, achieving a 15% size reduction through efficient component placement and routing while developing UPS logic with Op-Amps. Debugged and resolved 20+ design flaws related to signal integrity, power sequencing, and thermal management, enhancing system stability by 20%. Simulated Buck and Boost converters with PI control in MATLAB/Simulink and leveraged Machine Learning (ML) to accelerate parameter sweeps, ensuring less than 5% noise and stable load regulation.

Nano-Electronics and Computing Research Lab - SFSU

Developed a Python framework to automate SPICE simulations for distributed RC networks, enabling efficient extraction of propagation delay, slew rate, and tail characteristics under varying resistance, capacitance, and segment configurations. Implemented an admittance propagation algorithm to generate reduced-order RC interconnect models (Pi Model) with less than 5% error compared to full RC network simulations. Performed transient and data sweep analyses in HSPICE to benchmark the accuracy of reduced-order Pi models against full RC tree models for interconnect delay estimation, identifying scenarios requiring higher-order models.

San Francisco State University

Gujarat Technological University